Power devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in many fields, including motor control inverters, power supply applications for large capacity FPDs (Flat Panel Displays) and the like, and inverters for home electrical appliances such as air conditioners and lighting.
Conventionally, such power devices have been driven and controlled by an electronic circuit formed by combining semiconductor elements such as a photo coupler and electronic components such as a transformer. However, recent technological developments on LSI (Large Scale Integration) have put high-voltage integrated circuit devices with a rated voltage of up to 1200 V into practical applications.
FIG. 10 is a structural diagram of a main part that includes a power module forming a motor control inverter and a main circuit drive circuit (for example, see PTL 1). Power devices used to drive a three-phase motor 70 form a bridge circuit and are stored in the same package so as to have a structure as a power module 71.
In the FIG. 10, the power module 71 is composed of IGBTs as power devices and diodes. Alternatively, instead of the IGBTs, the power devices may be MOSFETs. In FIG. 10, the IGBTs are represented by upper arm output elements Q1 to Q3 and lower arm output elements Q4 to Q6, and the diodes are represented by D1 to D6.
A high potential-side terminal (=VCC2H terminal) of a main power supply VCC2 is connected to collectors of the Q1, the Q2, and the Q3, and a low potential-side terminal (=VCC2L terminal) thereof is connected to emitters of the Q4, the Q5, and the Q6.
A gate of each IGBT is connected to an output of a main circuit drive circuit 72, and outputs U, V, and W of the inverter formed by the power module 71 are connected to the three-phase motor 70.
The main power supply VCC2 supplies a high voltage of usually AC 100 to 400 V. Particularly, when each of the Q4, the Q5, and the Q6 is in an OFF state and each of the Q1, the Q2, and the Q3 is in an ON state, an emitter potential of each of the Q1, the Q2, and Q3 is at high voltage level.
Due to that, the gates of the elements, when driven, need to be driven at an even higher voltage than the emitter potential level.
In addition, input/output terminals I/O (Input/Output) of the main circuit drive circuit 72 are usually connected to a microcomputer that entirely controls the inverter circuit composed of the power module 71. There will be described an exemplary case in which the main circuit drive circuit 72 is composed of a high-voltage integrated circuit device.
FIG. 11 is a location diagram of a main part including each element in a case in which the main circuit drive circuit is composed of a high-voltage integrated circuit device. The main circuit drive circuit 72 transmits and receives signals to and from a microcomputer through the input/output terminals I/O. The main circuit drive circuit 72 includes a control circuit (CU: Control Unit) that generates a control signal for turning ON/OFF IGBTs. Additionally, the main circuit drive circuit 72 includes gate drive circuits (GDUs: Gate Driver Units) that receive a signal from the CU to drive the gates of the IGBTs and also detects overcurrent in the IGBTs to transmit an abnormal signal to the CU. Furthermore, the main circuit drive circuit 72 includes an LSU (level shift circuit) that serves to mediate a potential (=VCC2L) level of the VCC2L terminal and a potential (=VCC2H) level of the VCC2H terminal regarding gate signals and alarm signals of the Q1, the Q2, and the Q3 connected to the high potential-side among the IGBTs forming the bridge of FIG. 10.
The GDUs include a GDU-U, a GDU-V, and a GDU-W respectively connected to the Q1, the Q2, and the Q3 respectively and a GDU-X, a GDU-Y, and a GDU-Z respectively connected to the Q4, the Q5, and the Q6 respectively. The GDU-U, the GDU-V, and the GDU-W respectively are circuits whose U-OUT, V-OUT, and W-OUT terminals respectively are at reference potential. Next will be a description of one example of the LSU in the circuit.
FIG. 12 is a basic structure diagram of an LSU (a level shift circuit). The basic structure uses a high-voltage n-channel MOSFET 61 and a resistor RL1. The high-voltage n-channel MOSFET 61 serves to level-shift a signal S1 from a CU (a control circuit) and output it to a GDU-U, a GDU-V, and a GDU-W. In the LSU, a signal S2 to be input to an upper arm GDU is output from between the high-voltage n-channel MOSFET 61 and the resistor RL1.
The high-voltage n-channel MOSFET 61 used in the LSU is required to have a breakdown voltage of about from 600 to 1400 V equivalent to that of the IGBTs (the upper and lower arm output elements Q1 to Q6) that drive the three-phase motor 70.
Next, a description will be given of a conventional high-voltage integrated circuit device (an HV gate driver IC) in which a bootstrap system is formed on the same semiconductor substrate (see PTL 2).
FIG. 13 is a circuit structural diagram in a case in which the GDU-U that drives the upper arm output element Q1 of FIG. 10 and the GDU-X illustrated in FIG. 11, an LSU, and a bootstrap diode Db are integrated in one chip. Obviously, the GDU-V and the GDU-W have the same structure.
FIG. 14 illustrates a sectional view of a main part in a case in which the high-voltage integrated circuit device illustrated in FIG. 13 is formed on an epitaxial substrate. The diagram illustrates the GDU-U and the bootstrap diode Db illustrated in FIG. 13.
As for the LSU (the level shift circuit) described in FIG. 13, only a level shift circuit on the level up side is illustrated.
Here, operation of the bootstrap circuit will be described. A Vb voltage (voltage of C1) provides a power supply to the GDU-U. In general, the Vb voltage is set to about 15 V in order to surely enhance (full ON) the external IGBT (Q1) that the HV gate driver IC drives.
The Vb voltage is the voltage of a floating power supply, and a U-OUT voltage that has a rectangular waveform at high frequency is used as a reference potential. As illustrated in FIG. 13, the floating power supply is composed of a combination of the bootstrap diode Db and a bootstrap capacitor C1.
The bootstrap circuit operates when the gate of the low-side IGBT (Q4) is in an ON state and the U-OUT voltage drops to ground potential through the IGBT (Q4). At this time, the bootstrap capacitor C1 is charged by a VDD power supply as a low voltage power supply of 15 V through the bootstrap diode Db.
In addition, conversely, in a period of time when the gate of the high-side IGBT (Q1) is ON, the voltage of the U-OUT terminal becomes a voltage of the VCC2 terminal or a voltage higher than that due to a transitional surge current. Thus, a reverse breakdown voltage of the bootstrap diode Db is required to be set to a breakdown voltage value of about from 600 to 1400 V equivalent to the high-voltage n-channel MOSFET 61.
The bootstrap capacitor C1 used for charging here needs to have a large capacitance of 100 nF or more and thus can hardly be integrated. Due to this, it is common to use an externally-attached tantalum capacitor, ceramic capacitor, or the like.
PTL 3 suggests that the formation of a pn diode by using an SOI (Silicon on Insulator) substrate makes voltage resistance of a bootstrap diode higher and reduces hole leakage to the substrate.
In addition, PTL 4 discloses a SON (Silicon on Nothing) structure formation technique that does not cause cost increase and low reliability, in which a plurality of grooves are two-dimensionally formed in an array on a surface of a silicon substrate and then the silicon substrate is subjected to heat processing to change the plurality of grooves to a single planar cavity.
In addition, PTL 5 provides a method for manufacturing a low-cost and high-quality SON semiconductor substrate that includes a first step of implanting ion for forming a minute cavity in a desired region on a substrate and a second step of performing heat processing on the substrate with the minute cavity formed by the first step, in which the second step includes at least a high temperature heat processing step for exposing the substrate to a temperature of 1000° C. or higher. In addition, PTL 5 discloses a method that can manufacture a high performance high-voltage integrated circuit device by performing the above semiconductor substrate manufacturing method in steps of the method.
In addition, PTL 6 discloses a technique that can maintain high breakdown voltage when reverse breakdown voltage is applied and can prevent hole leakage to a substrate when charging a bootstrap capacitor, by locating a bootstrap diode in a high-voltage junction terminating region surrounding a high-side drive circuit unit and forming a cavity below an anode region and a cathode region of the diode.
In addition, PTL 7 discloses a bootstrap emulator function in which a bootstrap FET (a field-effect transistor) is located in a part of a high-voltage junction terminating region surrounding a high-side drive circuit unit and the gate of the FET is controlled at a timing when charging a bootstrap capacitor.
Additionally, PTL 8 describes a SOI lateral semiconductor device that can obtain high breakdown voltage and low switching loss even with the use of a thin buried oxide film formed by a SIMOX method. In the disclosure, a high-voltage IGBT and a MOSFET are arranged in parallel so as to vertically sandwich a buried oxide film of a partial SOI substrate formed by oxygen ion implantation.
In the structures illustrated in FIGS. 13 and 14, when the high-side (upper arm-side) IGBT (Q1) is turned OFF, the voltage of the U-OUT terminal is reduced to ground potential to charge the bootstrap capacitor C1. The bootstrap diode Db has a structure in which an n− layer as a Nepi layer and an n+ buried layer are provided on a p− substrate, and a p+ diffusion is formed as an anode diffusion region.
Accordingly, in a process for charging the bootstrap capacitor C1, while electrons are supplied from the anode electrode of the bootstrap diode Db to the VDD power supply, holes are supplied to a low-potential cathode electrode.
However, in a low voltage region where the bootstrap diode Db has a forward voltage drop (VF voltage) of 2 V or less, many holes pass through the buried layer to flow to the p− substrate at the ground potential. As a result, in the period of time in which the U-OUT voltage is reduced to the ground potential to charge the bootstrap capacitor, a large leakage current (leaked current) occurs in the GND terminal of the p− substrate of the HV gate driver IC from the high potential-side terminal of the VDD power supply, thereby increasing current consumption. PTL 6 previously cited also states that, in a period of time for charging the bootstrap capacitor, holes escape from an anode region-side (VDD) as the p+ region of the bootstrap diode Db to a p− substrate via an n+ buried layer to become a leakage current Ileak.
This occurs for the reason that a rate of hole components flowing in a direction of the p− substrate fixed at the ground potential where potential barrier is low is larger than a rate of holes injected from the anode region-side as the p+ region and taken into the cathode region-side as the n+ region to, as minority carriers, recombine with electrons, with the result that the holes become a leakage current to the p− substrate.
In addition, as illustrated in PTL 6 and PTL 7, in order to locate the bootstrap diode or the bootstrap FET element in the high-voltage junction terminating region surrounding the high-side drive circuit, typically, two high voltage n-channel MOSFETs (equivalent to 61 of FIG. 12) for a setting signal and a resetting signal need to be similarly located in the high-voltage junction terminating region. This imposes restriction on a location region for each.
The reason for that is as follows. While the high-voltage n channel MOSFET as the level shift element uses, as a backgate layer, the p-type GND region surrounding the periphery thereof and, as a drain drift layer, the n− region as a withstand voltage region surrounded by the p− region, the bootstrap diode is fixed at the VDD potential illustrated in FIG. 13 and the cathode region is connected to the U-VCC terminal similarly illustrated in FIG. 13. Accordingly, the high voltage n-channel MOSFET and the bootstrap diode cannot be located close to each other, and need to be sufficiently spaced apart from each other. Alternatively, an element separation structure is additionally needed, such as trench groove formation or formation of a diffusion layer for separation in each thereof. This leads to increase in chip area of the HV gate driver IC and increase in production cost.
FIG. 15 is a planar structural diagram of a case in which both of the high-voltage n-channel MOSFET and the bootstrap diode described in PTL 6 are located in the same high-voltage junction terminating region. As for potentials of a drain layer of a level shifter (the high-voltage n-channel MOSFET) and a cathode region 7K of the bootstrap diode illustrated in FIG. 15, there is a difference between the drain potential and the VCC potential, as described above. Accordingly, in order not to allow holes to be injected from an anode region 6A of the bootstrap diode to the drain layer in charging operation of the bootstrap diode, the drain layer and the anode region 6A are located at a distance of about several hundred μm from each other. Additionally, preferably, the cathode region 7K and the drain layer are also spaced apart from each other at a distance of about several hundred μm so that, for example, in such a reverse recovery state where the drain and the cathode region 7K are raised to high voltage, electron carriers substituted in the cathode region 7K are not mistakenly injected into the drain layer of the high voltage n-channel MOSFET. This is because, since the high voltage n-channel MOSFET is the level shift element, injection of the electron carriers to the drain layer leads to malfunction of the level shift circuit.
Here, the two elements, the high voltage n-channel MOSFET and the bootstrap diode, can be located in different high-voltage junction terminating regions. However, obviously, the locations thereof occupy an extra location area, thus inevitably increasing the chip area of the HV gate driver IC.
In addition, problems caused by locating both of the high-voltage n-channel MOSFET and the bootstrap diode in the same high-voltage junction terminating region include, besides electrical separation between the elements, reduction in charging ability of the bootstrap diode. In case of a level shift circuit with a two input system, two high voltage n-channel MOSFETs are needed for a setting signal and a resetting signal. Locating these elements in the high-voltage junction terminating region imposes restriction on location areas for the anode region and the cathode region of the bootstrap diode.
In cases of applications such as inverters used in home electrical appliances or the like operated with a low rated output, a power device (here, power MOSFET) has a small gate capacitance and a carrier frequency of about 100 KHz, and a bootstrap capacitor to be charged has a capacitance of about from 100 nF to 1 μF. Thus, a charging current of the diode in charging the capacitor may be of about several ten mA. However, in cases of applications including purposes requiring high frequencies of from 500 KHz to 1 MHz or the like and inverters for industrial equipment using power devices (here, IGBTs) with large gate capacitance, the capacitance of a bootstrap capacitor to be charged is about from several μF to several ten μF. Due to this, when charging the capacitor, the diode needs to supply about several hundred mA of charging current. In addition, a forward voltage (VF) at that time is around several V that is equivalent to a discharging voltage of the capacitor. Thus, in order to supply several hundred mA level of charging current, a drift resistance of the bootstrap diode needs to be reduced and a sufficient element area needs to be secured.